Don’t Just Test It,
GD4 Test It.
GD4 Test Services, Inc. (“GD4”) supports a full range of integrated circuit (IC) testing, programming and packing options.
GD4 is an independent, privately owned electronic component test lab with three U.S. locations: Austin, Texas (HQ and original test lab,) Largo, Florida; and Yaphank (Long Island,) New York.
All of our facilities are certified ISO 9001 / AS9100 and ISO 17025, AS6171 and AS6081. In addition, GD4 is also certified ANSI / ESD S20.20.
Extensive Testing Capabilities
(click on pics to view. click outside of pic to return to capability.)
Bake and Dry Pack
GD4 utilizes ESD protective packaging materials for ESD sensitive items. We strictly adhere to ANSI / ESD S20.20 industry standards to ensure safe handling, testing and return of your electronic components.
Bake and Dry Pack is an ideal way to guard and preserve moisture sensitive devices. All units requiring this service are baked according to the manufacturers’ MSL (moisture sensitivity level) specifications.
The devices are then dry packed within a vacuum-sealed, ESD-safe MSL bag accompanied by desiccant, a humidity indicator card (HIC) and an “MSL exposure warning” label.
GD4 provides its customers with evidential documentation through their supply chain as we process their material.
Bond Pull Testing
This service is a mechanical test process that evaluates the bond quality of the wire bonds within the component. It is used to verify bond consistency and reliability throughout the lot.
This process includes the bond wires being pulled or manipulated upward, perpendicular to the substrate until the wire breaks and/or bond failure occurs.
Thus, verifying that the applied force necessary is beyond the required standards. The entire process is performed in accordance with MIL-STD-883.
This process is a high-stress centrifugal test that simulates the effects of constant acceleration on integrated circuit (IC) components.
This is a mechanical process that can determine structural weaknesses in the package types which may not be detected through vibration or shock testing.
The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices.
If the leads are distorted, a number of them may end up above the surface. This deviation from flatness is referred to as “non-coplanarity.” The plane of the surface on which the package would naturally sit is called the ‘seating plane’.
This test is performed to confirm the device leads will line up and sit correctly in their final application.
Counterfeit Screening consists of a variety of key functional parameters developed and implemented by our engineers, per manufacturer specifications, to verify both authenticity and functionality of a device.
The counterfeit screening process will identify remarked and defective devices preventing them from entering or continuing through the supply chain.
Cross Section is a prepared electronics sample that allows analysis at a plane that cuts through the component sample. It is a destructive technique requiring a portion of the sample be cut or ground away to expose the internal plane for analysis. This process prepares the sample for inspection of quality assurance, supplier conformity, and failure analysis.
C-SAM Analysis (Confocal Scanning Acoustic Microscope)
Improper solder reflow techniques or improper handling of moisture-sensitive devices can cause delamination and/or voids which is a separation of the die from the molding compound.
C-SAM analysis is a screening technique that can uncover anomalies within a device’s package and construction through and to the die level.
C-SEM Analysis (Controlled Scanning Electron Microscope)
GD4 possesses a fully PC Controlled Scanning Electron Microscope (C-SEM).
It is utilized to investigate component surfaces at a high magnification (up to 100,000x) with a high depth of focus, for recording, archiving, processing and analysis of the magnified images in the standard image formats by means of the computer.
This includes scanning of the layers on MLCCs (multi layer chip capacitors.)
Decapsulation is a destructive die verification process that involves exposing the internal die of an IC or component.
This process allows us to microscopically reveal the manufacturer, date, internal part number and logos supplied by the original component manufacturer.
These markings can then be compared to top markings, a direct match, family of parts or a suspect part. When more than one device is decapped within a lot, the markings are compared to each other for homogeneity
At GD4, we are able to program or erase a variety of device types with manufacturer, customer or end user supplied programs.
We can also validate for previous programming (blank check,) which is particularly useful with One-Time Programmable (OTP) devices.
Supported Device Types: EPLD, FPGA, PALs, PROMs, EPROMs, EEPROMs, Flash and others.
Supported Device Packages: SOIC, TSOP, DIP, PLCC, BGA, QFP and others.
External Visual Inspection
GD4 performs a thorough visual inspection on all incoming material following IDEA 1010 and appropriate MIL-STD-883 standards.
Cross-referencing the original manufacturer’s datasheet specifications, our lab technicians examine external signs of re-working, prior use, damage, bends and breaks.
Our lab technicians will verify quantity, identify date codes and create a digital photographic record.
When parts are failing in their end applications, there can be many reasons. GD4 works with end user engineers to recreate the same operating conditions and to determine where failure is occurring.
Electrical testing can be used to determine the specific failing parameter(s). A variety of other processes such as C-SAM, Hermetic Seal testing, X-Ray, Decapsulation and more can be utilized to determine what the root cause of the failure may be.
This is a wholly customizable process. It can be uniquely tailored to the customer’s and device’s specific needs.
Heated Chemical Testing (HCT)
The heated chemical process removes the markings and top layer of the component. This allows our techs to inspect for signs of remarking. These signs can include: prior markings, sanding, pitting, differing body material or other evidence of tampering.
A submersion test utilizing 1-Methyl 2-Pyrrolidinone followed by Dynasolve removes the part markings and the top layer of the device. This process is very useful in counterfeit detection and is performed in accordance with MIL-STD-883, Method 2015.
Hermiticity and Fine / Gross Leakage
Hermeticity testing examines the effectiveness of the seal of the component package. Fine and Gross leakage testing processes can be used to test hermetic seal of the device(s).
A damaged seal may allow moisture and gases to travel to and from the package cavity freely through voids in the seal. This can result in internal corrosion and parametric shifts due to moisture effects.
It is therefore necessary to detect these failures so that affected materials may be properly quarantined and the root cause of the problem properly addressed.
This process is performed in accordance with MIL-STD-883, Method 1014.
Highly Accelerated Stress Testing (HAST)
The process of utilizing the Highly Accelerated Stress Test (HAST) is to combine high temperature, high humidity, high pressure and time to measure component reliability with or without electrical bias.
Under this controlled environment, HAST accelerates the stresses of the more traditional tests. This process acts as a corrosion failure test to essentially predict future functionality.
JAN / JANTX / JANS Screening
JAN, JANTX, and JANS diodes are specially designed for joint army and navy applications.
This specification establishes the general performance requirements for semiconductor devices. Detail requirements and characteristics are specified in the specification sheet.
GD4 can screen diodes of lower or unknown ratings to specific JAN/JANTX/JANS requirements.
Revisions to this specification and specification sheets are structured to assure the interchangeability of devices of the same part type regardless of manufacturing date code or conformance inspection (CI) completion date.
Five quality levels for encapsulated devices are provided in this specification, differentiated by the prefixes JAN, JANTX, and JANS.
Class JAN: Military level QCI Only
Class JANTX: Screening and QCI without Visual inspection
Class JANS: Highest Space level product
Life Test – essentially an electrical stress test which employs voltage and/or temperature to accelerate the appearance of wear-out reliability failures in a device.
Its objective is to evaluate whether failures caused by accelerated artificial wear is likely to occur during the product’s lifetime.
This process allows GD4 to estimate compliance of the device with the manufacturer’s long-term reliability requirement.
Resistance to Solvents
Resistance to Solvents (RtS) is a marking permanency test. The top side of devices are subjected to multiple chemicals and evaluated for part marking or body deviations and evidence of potential remarking.
This process uses a variety of solvents and is performed per MIL-STD-883 Method 2015, AS6171, AS6081 or to the requesting customer’s specific requirements.
Restriction of Hazardous Substances (RoHS) Compliance Testing
The Restriction of Hazardous Substances (RoHS) test screens electronic devices for certain hazardous heavy metals (such as lead, mercury, hexavalent chromium and cadmium) so that those metals do not find their way into landfills where they can adversely affect the environment.
Solderability testing is performed per MIL-STD-883. The device(s) endure a “Steam Age” process which artificially “ages” the leads of the device(s) ten years within eight hours.
Testing verifies whether the solder adheres to at least 95% of the usable area of the leads on a device or if it does not. This test is considered destructive.
Solder Dip is accomplished by submerging device leads into a molten solder bath. Thus, all lead surfaces are coated with filler metal.
GD4 is also able to convert the lead finish. For example, from lead-free to leaded or from leaded to lead-free. This method is used to improve/restore the solderability of the parts, and it can act as the primary finish for the terminations.
It is also one of the strategies used to mitigate tin whiskers, which can form when pure tin plating is used.
GD4 is capable of lead cleaning which involves cleaning the leads before solder dipping to ensure the solder adheres to the leads properly.
Temperature Cycle Testing
Temperature Cycle testing is considered a stress test. This process exposes the devices to extreme hot (-85 – 200 degrees C) and extreme cold temperature (-75 – 0 degrees C) thresholds at an accelerated rate.
When performed in conjunction with electrical and visual testing, it can help to find failures and determine the quality and longevity of the lot.
Many devices have multiple potential ratings, whether it be temperature (Commercial, Industrial, Military, etc.) or rated speed.
Due to availability constraints, users may procure material at a lower rating and have it tested at the more demanding rate their end application requires.
For example, utilizing Commercial-rated parts where the typical requirement may be Industrial-rated parts.
X-Ray is a relatively inexpensive process with minimal set-up and immediate feedback on the interior structure of a device.
It allows the operator to view the internal die orientation/size, bond wire patterns, lead frame patterns and inspect for any foreign material.
It can also help to detect any abnormalities without being destructive to the units.
Uniformity of internal structures is further evaluated among material within the same lot/batch. This process is performed in accordance with MIL-STD-883.